In the semiconductor industry, there is an incentive to reduce the size of each semiconductor device on a chip. For example, a smaller device can result in an increased density of devices on a chip and in a faster device. This allows increased functionality for a given size chip.
A smaller and faster MOSFET (metal oxide semiconductor field effect transistor) device may be realized by decreasing the channel length of the device. This generalization has its limits: as the channel length of a device is decreased beyond 0.1 .mu.m, for example, device performance may not improve. As known to those skilled in the art, deviations in performance may be due to an increased series resistance of the source and drain diffusion regions of the device.
When the channel length of a MOSFET device is reduced to improve device performance, it may not be possible to simply scale the source and drain diffusion regions in proportion to the channel length reduction. Deeper source and drain diffusion regions are desirable for making source and drain contacts without increasing junction leakage and for reducing source and drain region resistance. Shallower source and drain regions are desirable, however, to reduce short-channel effects such as the drain-induced barrier-lowering and the sub-threshold leakage current of the device.
FIG. 1 shows a device 100 with a gate formed upon a substrate 105. The device 100 of FIG. 1 has deep junctions 110, 120 to form contacts having low junction leakage and has shallow diffusion extensions 115, 125 to reduce the short-channel effects. The device 100 includes isolation regions 150; diffusion contacts 140, 142; oxide regions 132, 134, 136; oxide or nitride spacers 166, 168; and a gate comprising a gate oxide 130, a heavily doped polysilicon gate 164, a gate conductor such as WSi.sub.x (Tungsten Silicide) 162, and a nitride or oxide cap 160.
When the length of the channel 180 is reduced, the lengths of diffusion extensions 115, 125 are not scaled proportionately. This provides sufficient distance between the deep junctions 110, 120 to reduce short-channel effects across the channel 180. This also increases the series resistance, however, of the diffusion extensions 115, 125. The lengths of the diffusion extensions 115, 125 become significant compared to the length of the channel 180, and the increased series resistance of the diffusion extensions 115, 125 can result in performance degradation of the device 100.
FIG. 2 shows a device 200 formed upon a substrate 205. The device 200 uses raised source and drain diffusions 210, 220 to reduce problems associated with high series resistance of the source and drain diffusion regions and to reduce junction leakage caused by junctions with shallow source and drain diffusions. The device 200 includes isolation regions 250; oxide regions 232, 234, 236; diffusion contacts 240, 242; oxide or nitride spacers 266, 268; and a gate comprising a gate oxide 230, a heavily doped polysilicon gate 264, a gate conductor such as WSi.sub.x 262, and a nitride or oxide cap 260. The raised source and drain diffusions 210, 220 are formed by selective epitaxial (epi) silicon deposition. The selective epi process generally is prone to defect formation, causing diffusion-to-diffusion shorts as well as diffusion-to-gate shorts.
To overcome the shortcomings of conventional semiconductor devices, a new device is provided. An object of the present invention is to provide an improved semiconductor device that reduces short-channel effects. A related object is to provide a method of manufacturing such a semiconductor device. Another object is to provide a device having diffusions in the silicon substrate above the device channel area. Still another object is to provide a device suited for manufacture by a hybrid resist or phase-edge sub-lithographic technique. A further object of the present invention is to provide a method of controlling the length and thickness of diffusion extensions of a device.